1. Field
The embodiments discussed herein are related to a data transfer control apparatus, a data transfer control method, and a computer product that control a data transfer.
2. Description of Related Art
Conventionally, direct memory access (DMA) transfer technologies have been disclosed for high speed data transfer between memories. A direct memory access controller (DMAC) is used as a dedicated controller to execute the DMA transfer. The DMAC has a function of executing data transfer from memory to memory, or from memory to a peripheral device without passing through a CPU.
For example, among various types of multi-core processor systems, in a distributed-memory multi-core processor system having memories respectively corresponding to a core, calculation results obtained by each core are stored to the memory corresponding to the core. After the storage, the multi-core processor system executes a DMA transfer to the memory of a master core, using the DMAC. Alternatively, when a process assigned to a different core uses the calculation results, the multi-core processor system executes a DMA transfer to the memory corresponding to that core.
DMAC control has been disclosed where a CPU transfers small amounts of data or discrete data and the DMAC executes transfers of large amounts of continuous data, whereby, higher data transfer speeds are realized (see, e.g., Japanese Laid-Open Patent Publication No. 2007-58276).
Another technique of DMAC control has been disclosed where distributed shared memories are used to efficiently execute a pipeline process for a data transfer process executed by the DMAC and an image process executed by a CPU, using (see, e.g., Japanese Laid-Open Patent Publication No. 2008-90455).
However, with the techniques according to Japanese Laid-Open Patent Publication Nos. 2007-58276 and 2008-90455, the bus is occupied due to a burst transfer by the DMAC and the CPU stands by until completion of the transfer by the DMAC. Therefore, a problem arises that the throughput of the CPU is degraded. When an interruption process occurs, the CPU tries to read an interruption handler present on a memory. However, the CPU reads the interruption handler after the completion of the DMA transfer executed by the DMAC. Therefore, a problem arises in that responsiveness with respect to real-time processes is degraded.